Conventional random access memories store data in a volatile manner, that is, the stored data is lost when power is removed from the memory. In many applications it is necessary that data be stored for a period of time when power is not applied to the circuit. This is termed nonvolatile storge. An example of such a nonvolatile memory cell is shown in U.S. Pat. No. 4,203,158 entitled, "Electrically Programmable and Erasable MOS Floating Gate Memory Device Employing Tunneling and Method of Fabricating Same." Design objectives for nonvolatile memory cells include minimization of area to maximize cell density, minimizing the thin oxide area used for current tunneling to reduce the susceptibility of the cell to manufacturing defects and the improvement of the capacitive coupling between the control gate and floating gate of the cell to maximize efficiency of cell area and applied voltage with respect to the current tunneling element.
In view of the above design objectives and the limitations of prior art nonvolatile memory circuits, there exists a need for such a memory circuit which maximizes the coupling to the floating gate, reduces the area and pitch of the cell and improves the reliability characteristics of the memory cell.